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What are important topics in Computer System Architecture for GATE CS?

gATE Computer science

  • Swati
  • 13938 Views
  • 10 Answers
10 Answers
  • I am sharing the topics in decreasing order of importancebr /1.       Cache Memory  and Pipeliningbr /2.      Machine instructions and addressing modesbr /3.      Secondary Memory,I/O interfce(DMA,Interrupts)br /4.      ALU datapath,CPU control designbr /Majority of questions have been asked on first two topics..but you can expect questions from remaining topics too so you  should try to cover all topics:)br /!--[if gte mso 9]xml w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="true" DefSemiHidden="true" DefQFormat="false" DefPriority="99" LatentStyleCount="267" w:LsdException Locked="false" Priority="0" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Normal"/ w:LsdException Locked="false" Priority="9" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="heading 1"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 2"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 3"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 4"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 5"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 6"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 7"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 8"/ w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 9"/ w:LsdException Locked="false" Priority="39" Name="toc 1"/ w:LsdException Locked="false" Priority="39" Name="toc 2"/ w:LsdException Locked="false" Priority="39" Name="toc 3"/ w:LsdException Locked="false" Priority="39" Name="toc 4"/ w:LsdException Locked="false" Priority="39" Name="toc 5"/ w:LsdException Locked="false" Priority="39" Name="toc 6"/ w:LsdException Locked="false" Priority="39" Name="toc 7"/ w:LsdException Locked="false" Priority="39" Name="toc 8"/ w:LsdException Locked="false" Priority="39" Name="toc 9"/ w:LsdException Locked="false" Priority="35" QFormat="true" Name="caption"/ w:LsdException Locked="false" Priority="10" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Title"/ w:LsdException Locked="false" Priority="1" Name="Default Paragraph Font"/ w:LsdException Locked="false" Priority="11" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtitle"/ w:LsdExcepti--

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  • Data Structuresbr /One of the most important constant topics for GATE 2018 are – Recursion, Trees and Graphs.br /Maximum weightage is given to the topic of trees.br /Questions from all the levels can come from the topics Recursive functions and pointers.br /Easy Questions can be expected from the topics- Stacks, Queues and Linked Lists.br /Algorithmsbr /One of the most important constant topics for GATE 2018 are – Algorithm Analysis, Sorting Algorithms, Graph Algorithms and Heap Trees.br /Maximum weightage is given to the topic of Sorting Algorithms and Dynamic Programming.br /Questions from all the levels can come from the topics Divide and Conquer Algorithms & Greedy algorithms.br /Easy Questions can be expected from the topics- Divide and Conquer Algorithms.br /Operating Systemsbr /One of the most important constant topics for GATE 2018 are – CPU Scheduling Algos, Semaphores, Paging and Page replacement algorithms.br /Maximum weightage is given to the topic of Paging and Page replacement algorithms.br /Questions from all the levels can come from the topics Semaphores and Segmentation.br /Easy Questions can be expected from the topics- Disk Scheduling Algorithms and Deadlock.br /Engineering Mathematicsbr /One of the most important constant topics for GATE 2018 are – Matrix Determinant, Propositional Logic and Predicate Logic.br /Maximum weightage is given to the topic of Mathematical Logic and Linear Algebra.br /Questions from all the levels can come from the topics Probability and Predicate Logic.br /Easy Questions can be expected from the topics- Groups, Functions and Lattice Theory.br /Digital Logicbr /One of the most important constant topics for GATE 2018 are – Combinational Circuits and Minimization and Couters.br /Maximum weightage is given to the topic of Combinational Circuits.br /Questions from all the levels can come from the topics Sequential Circuits.br /Easy Questions can be expected from the topics- Number system, fixed and floating point registers.br /Computer Architecture and Organizationbr /One of the most important constant topics for GATE 2018 are – Pipelining and Cache Organization.br /Maximum weightage is given to the topic of Cache Organisation.br /Questions from all the levels can come from the topics Pipelining and I/O Data transfer.br /Easy Questions can be expected from the topics- Machine Cycles and Addressing modes.


  • Following Topics are important:br /1. Instruction set architecturebr /2. Pipeliningbr /3. Addressing modesbr /4. Cache Memory and its designbr /5. CPU design


  • Memorybr /Pipeliningbr /ALUbr /I/0br /Instruction set


  • Concepts of Computer Organisation, Architecture, Machine learning, formal languages and finite automata, graph theory are important


  • operating systembr /data structurebr /data basebr /mathematics.


  • ufollowing topic is most important for gate exam./ubr /1) Cache Memory  and Pipeliningbr /2) Machine instructions and addressing modesbr /3) Secondary Memory,I/O interfce (DMA,Interrupts)br /4) ALU datapath,CPU control designbr /Majority of questions have been asked on first two topics..but you can expect questions from remaining topics too so you  should try to cover all topics.


  • Computer Organization and Architecturebr /Machine instructions and addressing modes. ALU, data‐path and control unit. Instructionbr /pipelining. Memory hierarchy: cache, main memory, and secondary storage; I/Obr /interface (Interrupt and DMA mode).br /1.      Cache Memory  and Pipeliningbr /2.      Machine instructions and addressing modesbr /3.      Secondary Memory,I/O interface(DMA,Interrupts)br /4.      ALU datapath, CPU control design


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  • especially numerical part ..i.e.cache and addressing modes

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